This disclosure relates to a decoder circuit for decoding a pulse amplitude modulation signal having multiple signal levels. In particular, this disclosure relates to a decoder circuit for decoding a broadband pulse amplitude modulation signal transmitted over optical links, a broadband pulse amplitude modulation signal in the field of backplane appliances and a broadband pulse amplitude modulation signal in similar applications.
In telecommunications, a non-return-to-zero (NRZ) signal enables encoding of bit streams, wherein the ones of the bit stream are represented by one significant condition, such as a positive voltage, and the zeros of the bit stream are represented by another significant condition, such as a negative voltage. The NRZ signal has no other neutral or rest condition. NRZ is a form of pulse amplitude modulation (PAM), where message information is encoded into the amplitude of signal pulses. NRZ refers to a modulation where one bit at a time is mapped into two possible signal amplitudes. PAM-4 refers to a modulation where two bits at a time are mapped into four possible signal amplitudes. For a given baud rate, PAM-4 can transmit up to twice the number of bits as NRZ. Correspondingly, a PAM-8 refers to a modulation where three bits at a time are mapped into eight possible signal amplitudes. For a given baud rate, PAM-8 can transmit up to three times the number of bits as NRZ. Other signals than NRZ, PAM-4 or PAM-8 are possible, such as PAM-12, PAM-16, etc.
In a PAM-4 based link, on the transmitting end, an encoder may combine two bit streams and create a single four-level signal, which is the PAM-4 signal. One of the bit streams corresponds to a Most Significant Bit (MSB). The other of the bit streams corresponds to a Least Significant Bit (LSB). On the receiving end, a decoder circuit may separate the PAM-4 signal into the two individual bit streams corresponding to the MSB and the LSB.
In an alternative embodiment, on the transmitting end, an encoder may encode a single bit stream into a PAM-4 signal.
In an alternative embodiment, on the receiving end, a decoder circuit may decode a PAM-4 signal into a single bit stream.
In an alternative embodiment, such as in the case of a repeater, a device may have an input for receiving a PAM-4 signal and an output for transmitting a PAM-4 signal, wherein the device may include at least a decoder circuit for decoding the received PAM-4 signal.
FIG. 1 illustrates a PAM-4 coding table, which defines the mapping of an MSB and an LSB into the PAM-4 signal levels. The combination MSB=1, LSB=1 is encoded into the PAM-4 signal level L3. The combination MSB=1, LSB=0 is encoded into the PAM-4 signal level L2. The combination MSB=0, LSB=1 is encoded into the PAM-4 signal level L1. The combination MSB=0, LSB=0 is encoded into the PAM-4 signal level L0.
FIG. 2 illustrates a PAM-4 coding example of a sequence of MSBs and a sequence of LSBs encoded into the PAM-4 signal levels. In the illustrative example according to FIG. 2, the PAM-4 signal includes the sequence of the signal levels L1, L0, L2, L3, L2, L3, L0, L0, L1.
FIG. 3 illustrates a PAM-4 output eye diagram, wherein the horizontal axis refers to time, and wherein the vertical axis refers to the PAM-4 signal levels L0, L1, L2, and L3. For a baud rate of 28 GBd/s, the symbol duration T is about 36 ps. For a baud rate of 56 GBd/s, the symbol duration T is about 18 ps. As illustrated in the eye diagram, between successive symbols, any change in the level of the PAM-4 signal is possible, including that the level of the PAM-4 signal does not change between successive symbols. As illustrated in FIG. 3, the first signal level L 1 is larger than the zeroth signal level, the second signal level L2 is larger than the first signal level L1, and the third signal level L3 is larger than the second signal level L2.
FIG. 4 illustrates a decoder circuit T′ for decoding a PAM-4 signal into a LSB bit stream and an MSB bit stream. As illustrated in FIG. 4, the PAM-4 signal includes four signal levels L0, L1, L2, L3. The decoder circuit T′ includes a decision block D′ and a logic circuit L′.
As illustrated in FIG. 4, the decision block D′ includes three decision circuits dA, dB, dC, which are denominated with labels A, B, C.
In some disclosures, decision circuits, such as the decision circuits dA, dB, dC illustrated in FIG. 4 and the first decision circuit d1 and the second decision circuit d2 described further below, are denominated as quantizers or similar.
In an embodiment, each of the decision circuits dA, dB, dC receives an input voltage. If the input voltage is below a threshold, such as −1.5 volts, 0.0 volts, +1.0 volts, etc., the respective decision circuit dA, dB, dC generates a low output signal, such as −1.0 volts, −5.0 volts, etc. If the input voltage is above the threshold, the respective decision circuit dA, dB, dC generates a high output signal, such as +1.0 volts, +5.0 volts, etc.
The decision circuit dA denominated with label A detects if the signal level of the PAM-4 signal is below or above the threshold th1, wherein the threshold th1 is the signal level in the middle between PAM-4 signal level L0 and PAM-4 signal level L1. If the signal level of the PAM-4 signal is below the threshold th1, the decision circuit dA denominated with label A generates a low output signal low_A denominated with label A. If the signal level is above the threshold th1, the decision circuit dA generates a high output signal high_A denominated with label A.
Thus, as illustrated in FIG. 4, if the decision circuit dA denominated with label A generates the low output signal low_A denominated with label A, the PAM-4 signal level is detected to be signal level L0. If the decision circuit dA denominated with label A generates the high output signal high_A denominated with label A, the PAM-4 signal level is detected to be either signal level L3, L2, or L1.
As illustrated in FIG. 4, the decision circuit dB denominated with label B and the decision circuit dC denominated with label C operate correspondingly to the decision circuit dA denominated with label A. The decision circuit dB denominated with label B generates a low output signal low_B denominated with label B in case the signal level of the PAM-4 signal is below the second threshold th2, which is the signal level in the middle between the PAM-4 signal level L1 and the PAM-4 signal level L2. The decision circuit dB denominated with label B generates a high output signal high_B denominated with label B in case the signal level is above the second threshold th2. Correspondingly, the decision circuit dC denominated with label C generates a low output signal low_C denominated with label C in case the signal level is below the third threshold th3, which is the signal level in the middle between the PAM-4 signal level L2 and the PAM-4 signal level L3. The decision circuit dC denominated with label C generates a high output signal high_C denominated with label C in case the signal level is above the third threshold th3.
Thus, as illustrated in FIG. 4, if the decision circuit dB denominated with label B generates the low output signal low_B denominated with label B, the PAM-4 signal level is detected to be either signal level L1 or L0. If the decision circuit dB denominated with label B generates the high output signal high_B denominated with label B, the PAM-4 signal level is detected to be either signal level L3 or L2.
Moreover, as illustrated in FIG. 4, if the decision circuit dC denominated with label C generates the low output signal low_C denominated with label C, the PAM-4 signal level is detected to be either signal level L2, L1 or L0. If the decision circuit dC denominated with label C generates the high output signal high_C denominated with label C, the PAM-4 signal level is detected to be signal level L3.
Only in case of the low output signal low_A denominated with label A and the high output signal high_C denominated with label C, the PAM-4 signal level can be directly detected to be signal level L0 or L3. In order to detect the PAM-4 signal level L1 and L2, further processing of the high output signal high_A denominated with label A, the low output signal low_B denominated with label B, the high output signal high_B denominated with label B, and the low output signal low_C denominated with label C is required.
Thus, as illustrated in FIG. 4, a logic circuit L′ with a two-level combinatorial logic is required in order to obtain the LSB and MSB bit streams. However, with limited power, a two-level combinatorial logic cannot run at high baud rates such as 28 GBd/s or 25 GBd/s. At high baud rates such as 28 GBd/s or 25 GBd/s, power consumption of a two-level combinatorial logic is high.
In a PAM-4 signal, the PAM-4 signal levels L0, L1, L2, L3 can have specific values, such as −2.0, −1.0, 1.0, 2.0, for example. The values −2.0, −1.0, 1.0, 2.0 can have a specific unit, such as volts, for example. Thus, the signal level L0 may correspond to −2.0 volts, the signal level L1 may correspond to −1.0 volts, the signal level L3 may correspond to +1.0 volts, and the signal level L3 may correspond to +2.0 volts. Moreover, the second threshold th2 may correspond to 0.0 volts, the first threshold th1 may correspond to −1.5 volts, and the third threshold may correspond to +1.5 volts.
The decision block D′ has the disadvantage that the design of the decision circuit dA denominated with label A and the decision circuit dC denominated with label C is particularly difficult. The design of the decision circuit dB denominated with label B is less difficult, because the decision as regards threshold th2 can be simply based on an average signal level. However, such a simple implementation is not possible for the decision circuit dA denominated with label A nor for the decision circuit dC denominated with label C.
Thus, decoding a PAM-4 signal as illustrated in FIG. 4 has the disadvantages that: (1) the design of the decision block D′, in particular the design of decision circuits dA, dC denominated with labels A,C, is difficult and that (2) an additional two-level combinatorial logic circuit L′ is required in order to determine the PAM-4 signal levels and to decode the PAM-4 signal, which requires high power at high baud rates.
US20150055694 relates to a phase detector having a detection logic for detecting data in a communication signal, amplitude detection logic for processing modulation of a PAM-2 and/or a PAM-4 communication modality, in-phase edge detection logic, quadrature edge detection logic, and a mixing logic for determining an amount of in-phase edge information and quadrature edge information to be applied based on at least one channel parameter in the communication channel.
U.S. Pat. No. 7,283,596 discloses a PAM-4 data slicer which includes a first, second, and third comparator which provide first, second, and third thresholds. Each comparator has an offset. The first and third comparators have an offset generating arrangement at their outputs to provide the first and third comparator circuits with symmetrical offsets.
U.S. Pat. No. 7,505,541 discloses a multi-mode phase and data detector. Based on a selectable bias level, latched comparators operate to detect the multi-level input data signal as it crosses a plurality of threshold levels. Logic selects subsets of exclusive OR gates and subsets of latching comparators to place the multi-mode phase and data detector in a PAM-4, NRZ, or PRML mode of operation.